A conventional multiported SRAM is described in "A 2.2 W, 180 MHz Superscalar RISC Microprocessor," by Gerosa et al, IEEE Journal of Solid-State Circuits, vol. 29, No. 12, December 1994. Another conventional multiported SRAM array is shown in U.S. Pat. No. 5,177,706, "Semiconductor Memory Device Having a Plurality of Ports, issued Jan. 5, 1993 to Shinohara et al. An example of a geometry of a standard approach is shown in FIG. 1, where a 4 read-port array is composed of a 4.times.4 array of cells (10, 11, 12, 13, . . . ). As depicted, a representative core cell 10, includes a data latch function 100 connected to 4 access means (110, 111, 112, 113), which are symbolically represented as logical AND functions. Each AND function is gated by one of the word lines (131, 132, 133, 134) to couple a value held in a data latch 100 to one of the four bit lines (121, 122, 123, 124). The activation of one of the word lines results in the coupling of the 4 bits on a port word line to each of the four port bit lines, one of which is selected by asserting an appropriate select signal 140 on one of the 4 multiplexers (150, 151, 152, 153). Sense amplifiers (160-175) are connected to each of the bit lines for detecting and amplifying the stored data. This effectively results in selecting one of 16 bits for each read port depending on the address presented to the bit and word line decoders. It is obvious that this structure can be conventionally replicated to achieve a realistic array size, by connecting N in parallel to achieve a N bit word readout and stacking M vertically to achieve the required capacity. Using a small (e.g., 4.times.4) sub-array keeps the number of bits per bit-line small and therefore speeds up the read time. The number of bits per row or column can also be adjusted to fit the desired parameters of the array.
A disadvantage to the conventional approach lies in the number of decoders, readout devices and sense amplifiers needed. Each port must have a sense amplifier per bit and a readout means per cell. For a differential readout (i.e., bit and not bit per port), 2 transistors are required per port per bit. In addition, a bit line (121 . . . 124) must exist for each port for each column of the array. In FIG. 1, for example, 16 bit cells require 128 transistors for readout on 4 bit line pairs per column. The core cells of the 16 bit to array only require 64 transistors in the smallest embodiment.
Thus there is a need for an improved multi-port SRAM (static random access memory) array, which requires fewer components--e.g., access transistors, bit lines and sense amplifiers--for multiport access. The SRAM should provide an efficient means to select a correct access device among the plurality of access devices within the array and to condition the correct multiplexer select signal to couple the correct bit as specified by the port read address to the port read output. The present invention addresses these needs.